Semiconductor memory device

ABSTRACT

Provided is a semiconductor memory device, which is capable of further simplifying the data multiplexing structure on a data write path, thereby preventing a timing mismatch in data input from being occurred. The semiconductor memory device, which comprises a data inputting block  30  for transferring data applied to a plurality of data input/output pins DQ 0  to DQ 15  to a plurality of global I/O buses gio&lt; 0:15 &gt;, a data multiplexing block  32  for multiplexing the data carried on the plurality of global I/O buses gio&lt; 0:15 &gt; according to a data width option, and a main write driver  34 , in response to a control signal, for driving the data outputted from the multiplexing means to a memory core region.

FIELD OF INVENTION

The present invention relates to a design technique for a semiconductormemory device; and, more particularly, to a data write path of thesemiconductor memory device.

DESCRIPTION OF PRIOR ART

Typically, a data bus, which transfers data inputted thereto via datainput/output pins (DQ) to a memory cell array, is referred to as aglobal I/O bus (GIO). Included within the memory cell array is ahierarchical I/O bus structure for transferring data between each bitline and the global I/O bus.

Meanwhile, a write driver is used to drive data carried on the globalI/O bus to the I/O bus within the memory cell array, and an I/O senseamplifier (IOSA) is used to transfer the data carried on the I/O buswithin the memory cell array to the global I/O bus.

In addition, a data input buffer, a data multiplexer, a data inputdriver and the like are disposed at a region of peripheral circuitry toconstitute a data write path of the semiconductor memory device. In caseof a semiconductor memory device such as DDR SDRAM, 16 data input/outputpins (DQ) and 16 global I/O buses (GIO) are provided to support X4, X8,and X16 data width options. Accordingly, when the X16 mode is selected,the data transmission is performed through each of the data input/outputpins (DQ) and each of the global I/O buses (GIO) corresponding thereto.However, when the ×4 mode or the ×8 mode is selected, a multiplexingprocess is required to transfer data inputted thereto via the datainput/output pins (DQ) to a particular global I/O bus(GIO), since thedata input/output pins (DQ) and the global I/O buses (GIO) does notcorrespond each other by one-to-one. Such function is performed by thedata multiplexer (an ×4 data multiplexer and an ×8 data multiplexer).

FIG. 1 is a circuit diagram of the ×4 data multiplexer according to theprior art.

Referring to FIG. 1, the ×4 data multiplexer 10 of the prior artincludes 4 pass gates PG1, PG2, PG3 and PG4 which selectively transferinput data din<0:3> to a global I/O bus gio<0>, in response to a controlsignal gayBD<0:3>.

Meanwhile, a plurality of the ×4 data multiplexers 10 is required tosupport the ×4 mode, each having the same configuration. Similarly, aplurality of the ×8 data multiplexers is required to support the ×8mode.

FIG. 2 is a block diagram which illustrating the data write pathaccording to the prior art.

Referring to FIG. 2, the data write path of the prior art includes: adata input block 20, which has a plurality of data input/output pins DQ0to DQ15, a plurality of ×4 data multiplexers MUX ×4, and a plurality of×8 data multiplexers MUX ×8, for transferring data applied thereto viathe plurality of data input/output pins DQ0 to DQ15, to the global I/Obuses gio<0:15>; and a main write driving block 25, which has aplurality of write drivers wd0 to wd15, for driving data carried on theglobal I/O buses gio<0:15> to the memory cell array, respectively.

In practice, although it is omitted in FIG. 2, the data input block 20includes a data input buffer for buffering the data applied to the datainput/output pins DQ0 to DQ15, and a data input driver for driving theglobal I/O buses gio<0:15> with the output signal of the datamultiplexers MUX ×4 and MUX ×8.

As demonstrated above, the data write path of the prior art includes theplurality of data multiplexers for supporting the data width option forthe data input block 20 disposed at the region of the peripheralcircuitry. As can be seen from FIG. 1, the prior art suffers from thedisadvantage that the data multiplexers MUX ×4 and MUX ×8 areintricately connected with the data input/output pins DQ0 to DQ15,resulting in greater layout area requirements.

Meanwhile, since several addresses should be inputted to control thedata multiplexers MUX X4 and MUX X8 in synchronism with a data inputtiming, the prior art suffers from the disadvantage that the probabilityof occurrence of a timing mismatch in data input increases.

SUMMARY OF INVENTION

It is, therefore, a primary object of the present invention to provide asemiconductor memory device, which is capable of further simplifying thedata multiplexing structure on a data write path, thereby preventing atiming mismatch in data input from being occurred.

In accordance with a preferred embodiment of the present invention,there is provided to a semiconductor memory device, which comprises: adata inputting means for transferring data applied to a plurality ofdata input/output pins to a plurality of data buses; a data multiplexingmeans for multiplexing the data carried on the plurality of data busesaccording to a data width option; and a write driving means, in responseto a control signal, for driving the data outputted from themultiplexing means to a memory core region.

In the present invention, a scheme is employed, which disposes a datamultiplexing structure for the data width option at the side of a mainwrite driver. Specifically, the scheme is not multiplexing data appliedto the data input/output pins (DQ) but multiplexing data carried on theglobal I/O buses (GIO). In this case, the total number of themultiplexers is decreased, and input to the multiplexers is simplified,thereby resulting in a dramatically reduced layout area and preventing atiming mismatch in data input from being occurred.

BRIEF DESCRIPTION OF DRAWINGS

The above and other objects and features of the present invention willbecome apparent from the following description of preferred embodimentsgiven in conjunction with the accompanying drawings, in which:

FIG. 1 is a circuit diagram of the ×4 data multiplexer according to theprior art;

FIG. 2 is a block diagram which illustrating the data write pathaccording to the prior art;

FIG. 3 is a block diagram of a data write path in accordance with apreferred embodiment of the present invention; and

FIG. 4 is a circuit diagram illustrating a portion of the configurationof the data multiplexing block and the main write driving block 34 shownin FIG. 3.

DETAILED DESCRIPTION OF THE INVENTION

Hereinafter, a semiconductor memory device according to the presentinvention will be described in detail referring to the accompanyingdrawings

FIG. 3 is a block diagram of a data write path in accordance with apreferred embodiment of the present invention.

Referring to FIG. 3, the data write path in accordance with a preferredembodiment of the present invention comprises: a data input block 30 fortransferring data applied to data input/output pins DQ0 to DQ15 toglobal I/O buses gio<0:15>; a data multiplexing block 32 formultiplexing data carried on the global I/O buses gio<0:15> according todata width options ×4, ×8 and ×16; and a main write driving block 34 fordriving data outputted from the data multiplexing block 32 to a memorycell array (memory core region) in response to a control signalgayBD<0:3>.

Herein, the data input block 30 includes the plurality of datainput/output pins DQ0 to DQ15, a plurality of data input buffers (notshown) for buffering the data applied to the data input/output pins DQ0to DQ15, and a plurality of pass gates PGs having the output of each ofthe data input buffers as its input, and a data input driver (not shown)for driving the global I/O buses gio<0:15> with the output of each ofthe plurality of pass gates PGs.

FIG. 4 is a circuit diagram illustrating a portion of the configurationof the data multiplexing block 32 and the main write driving block 34shown in FIG. 3.

Referring to FIG. 4, the data multiplexing block 32 includes: an ×16selecting block 40 for selectively outputting the data carried on theglobal I/O buses gio<0:15> in response to an ×16 option selection signal×16; an ×8 selecting block 42 for selectively outputting 8 of the datacarried on the global I/O buses gio<0:15> in response to an ×4/×8 optionselection signal ×4/×8 and ×8 option selection signal ×8; and an ×4selecting block 44 for selectively outputting 4 of the data outputtedfrom the ×8 selecting block 42 in response to the ×4 option selectionsignal ×4.

In FIG. 4, only the multiplexing structure corresponding to 4 global I/Obuses gio<0:3> is shown, thus required are 4 circuits with the sameconfiguration as the circuit shown in FIG. 4. A detailed descriptionwill be made as to a circuit configuration of ¼ circuit as shown in FIG.4, e.g., the data multiplexing block 32.

First, the ×16 selecting block 40 includes 4 pass gates PG11, PG12, PG13and PG14 for selectively passing the data carried on each of the globalI/O buses gio<0:3>, under the control of the ×16 option selection signal×16 which is activated upon the selection of the ×16 data width option.

Next, the ×8 selecting block 42 includes: a NAND gate NAND1 having the×4/×8 option selection signal ×4/×8 which is activated upon theselection of the ×4 or ×8 option selection signals, and the data carriedon the global I/O buses gio<0> and gio<1> as its input; an inverter INV1having the output of the NAND gate NAND1 as its input; a pass gate PG21for selectively passing the output signal of the inverter INV1 inresponse to the ×8 option selection signal ×8 which is activated uponthe selection of the ×8 data width option; a NAND gate NAND2 having the×4/×8 option selection signal ×4/×8 and the data carried on the globalI/O buses gio<2> and gio<3> as its input; and a pass gate PG22 forselectively passing the output signal of the inverter INV2 in responseto the ×8 option selection signal ×8.

Next, the ×4 selecting block 44 includes: a NAND gate NAND3 having the×4 option selection signal ×4 which is activated upon the selection ofthe ×4 data width option and the output signals of the inverters INV1and INV2, as its input; an inverter INV3 having the output of the NANDgate NAND3 as its input; and a pass gate PG31 for selectively passingthe output signal of the inverter INV3 in response to the ×4 optionselection signal ×4.

Meanwhile, the main write driving block 34 includes 4 write drivers WD0,WD1, WD2 and WD3, which drives the output signal of the datamultiplexing block 32 in response to the control signal gayBD<0:3> tolocal buses lio<0:3>, liob<0:3> within the memory cell array, whereinthe output signal is one of the output signals gio_(—)×16<0:3> of the×16 selecting block 40, the output signals gio_(—)×8<0:1> of the ×8selecting block 42, and the output signal gio_(—)×16<0> of the ×4selecting block 44.

Note that the configuration of the data multiplexing block 32 and themain write driving block 34 described above corresponds to that of 4global I/O buses gio<0:3> of the 16 global I/O buses gio<0:15>, threecircuits with the same configuration as the circuit shown in FIG. 4 arerequired.

A detailed description will be made as to the operation of the datawrite path in accordance with the present invention with reference toFIGS. 3 and 4.

First, referring to FIG. 3, the data applied to the data input/outputpins DQ0 to DQ15 is carried on the global I/O buses gio<0:15>corresponding to each of the data input/output pins DQ0 to DQ15irrespective of the data width option, since separate multiplexingstructure is not provided to the data input block 30.

Meanwhile, referring to FIG. 4, each of the pass gates PG11, PG12, PG13and PG14 of the ×16 selecting block 40 in the data multiplexing block 32passes the data carried on the global I/O buses gio<0:3> upon theselection of the ×16 data width option, and blocks the data upon theselection of the ×4 or ×8 data width options. In this case, the writedrivers WD0, WD1, WD2 and WD3 in the main write driving block 34 receivethe data gio_(—)×16<0:3> outputted from the ×16 selecting block 40respectively, and are enabled by the control signal gayBD<0:3>, therebyallowing the input data to be driven to the local I/O buses lio<0:3> andliob<0:3> within the memory cell array, respectively.

Subsequently, upon the selection of the ×8 data width option, the ×8selecting block 42 passes data carried on one corresponding to the datainput/output pins to which external data is applied, among a pair ofglobal I/O buses gio<0:1> and gio<2:3>. In this case, the othercorresponding to the data input/output pins being not in use at the ×8data width option holds in a high logic level. The pair of write driversWD0, WD1, WD2 and WD3 in the main write driving block 34 receives thedata gio_(—)×8<0> and gio_(—)×8<1> outputted from the ×16 selectingblock 40 and is enabled one at a time in response to the control signalgayBD<0:3>, thereby allowing the input data to be driven to acorresponding local I/O bus.

Subsequently, upon the selection of the ×4 data width option, the ×4selecting block 44 passes data carried on one corresponding to a datainput/output pin to which external data is applied, among 4 global I/Obuses gio<0:3>. Even upon the selection of the ×4 data width option, the×4/×8 option selection signal ×4×8 is activated. As a result, the ×4selecting block 44 is capable of receiving data provided at the front ofthe pass gates PG21 and PG22 of the ×8 selecting block 42. In this case,the other corresponding to the data input/output pin being not in use atthe ×8 data width option holds in a high logic level. The 4 writedrivers WD0, WD1, WD2 and WD3 in the main write driving block 34 receivethe data gio_(—)×4<0> outputted from the ×4 selecting block 44 and areenabled one at a time in response to the control signal gayBD<0:3>,thereby allowing the input data to be driven to a corresponding localI/O bus.

In the overall circuit, when the ×16 data width option is selected, 16local I/O buses are driven; when the ×8 data width option is selected, atotal of 8 local I/O buses as once per two local I/O buses are driven;and when the ×4 data width option is selected, a total of 4 local I/Obuses as once per four local I/O buses are driven.

As can be seen from the foregoing descriptions, the present inventionemploys the scheme which disposes the data multiplexing structure forthe data width option at the side of the main write driver.

As mentioned above, if used is the scheme which is not multiplexing thedata applied to the data input/output pins DQ but multiplexing the datacarried on the global I/O buses GIO, the input structure of themultiplexer is simplified, which in turn results in a simplifiedcircuit, thereby leading a dramatically reduced layout area. Further,the input of a plurality of addresses for multiplexing control to thewrite driver ensure a timing margin between the data inputs, therebypreventing a timing mismatch in data input from being occurred.

For example, in the abovementioned embodiments, even though there isillustratively described with respect to the semiconductor memory devicesupporting ×16/×8/×4 data width options, the present invention may beapplied to the case that the semiconductor memory device furthersupports an ×32 data width option. In this case, one stage is added tothe data multiplexing block.

Therefore, the present invention simplifies the multiplexing structureon a data write path to reduce a layout area and prevents a timingmismatch in data input from being occurred, which, in turn, improvesreliability of the semiconductor memory device.

The present application contains subject matter related to Korean patentapplication No. 2003-86265, filed in the Korean Patent Office on Dec. 1,2003, the entire contents of which being incorporated herein byreference.

While the present invention has been described with respect to theparticular embodiments, it will be apparent to those skilled in the artthat various changes and modification may be made without departing fromthe spirit and scope of the invention as defined in the followingclaims.

1. A semiconductor memory device, which comprises: a data inputtingmeans for transferring data applied to a plurality of data input/outputpins to a plurality of data buses; a data multiplexing means formultiplexing the data carried on the plurality of data buses accordingto a data width option; and a write driving means, in response to acontrol signal, for driving the data outputted from the multiplexingmeans to a memory core region.
 2. The semiconductor memory device ofclaim 1, wherein the data multiplexing means includes: an X16 selectingblock for selectively outputting the data carried on the data buses inresponse to an X16 option selection signal X16; an X8 selecting blockfor selectively outputting eight of the data carried on the data busesin response to an X4/X8 option selection signal X4/X8 and an X8 optionselection signal X8; and an ×4 selecting block for selectivelyoutputting four of the 8 data outputted from the X8 selecting block, inresponse to the ×4 option selection signal X4.
 3. The semiconductormemory device of claim 1, wherein the data inputting means includes: aplurality of data input/output pins; a plurality of data input buffersfor buffering data applied to the plurality of data input/output pins;and a plurality of pass gates having output of each of the plurality ofdata input buffers as its input; and a data input driver for driving theplurality of data buses with output of each of the plurality of passgates.
 4. The semiconductor memory device of claim 1, wherein each ofthe write driving means includes a plurality of write drivers fordriving the output signal of the data multiplexing means to a bus in thememory core region, in response to the control signal.
 5. Thesemiconductor memory device of claim 2, wherein the ×16 selecting blockincludes first to sixteen pass gates for selectively passingtherethrough the data carried on each of the data buses, in response tothe ×16 option selection signal ×16.
 6. The semiconductor memory deviceof claim 5, wherein the ×8 selecting block includes: 1st to 8th NANDgates having the ×4/×8 option selection signal and the data carried ondifferent pairs of the data buses as its input, respectively; 1st to 8thinverters having the output signals of the 1st to 8th NAND gates as itsinput, respectively; and 17th to 24th pass gates having the outputsignals of the 1st to 8th inverters as its input respectively, and iscontrolled by the ×8 option selection signal.
 7. The semiconductormemory device of claim 6, wherein the ×4 selecting block includes: 9thto 12th NAND gates having the ×4 option selection signal ×4 and theoutput signal of different pairs of the 1st to 8th inverters as itsinput, respectively; 9th to 12th inverters having the output signals ofthe 9th to 12th NAND gates as its input, respectively; and 25th to 28thpass gates having the output signals of the 9th to 12th inverters as itsinput respectively, and is controlled by the ×4 option selection signal×4.